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Scott Hauck Gaetano Boriello Steven Burns Carl Ebeling
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Actel adders algorithm application ASIC ASIC design asynchronous circuits Boolean relation chip CLBs complex configuration connected decoder delay design flow deterministic test patterns elements emulator EPROM Field Programmable Gate Field-programmable gate arrays FIFO Figure flexible FPGA FPGA devices function fuzzy hardware expense HardwareC high level high level synthesis IEEE implementation input instruction interface Kohonen logic blocks logic cell logic synthesis machine manual design mapping matrix memory minimization modules MPGA NAND netlist nodes one-hot operations optimization ORCA output performance placement problem Proceedings processor product terms Programmable Gate Arrays Queue rapid prototyping real-time reconfigurable routing sequence signal SIMD simulation speed squarers SRAM-based FPGAs structure synthesis tool systolic array task test patterns tree searching unit variables vectors verification VHDL VHDL code Viewlogic VLSI XCircal Xilinx Xputer