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CESARA Programmable Systolic Array Multiprocessor System
discussed in Session
Performance of VHSIC Devices in High Throughput Signal Processing
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algorithm allocation applications architecture array assigned Boolean cell chip CITO clause communication compiler components concurrent configuration connected cycle data flow database dataflow delay developed device DICOMED dynamic efficient equations evaluation example execution fault Figure ﬁle ﬁrst Fortran function global graph hardware IEEE IEEE Trans image processing implementation input instruction interconnection interface iteration language Load logic loop machine Mahalanobis Distance matrix memory method MIMD module Monitor multiple multiprocessor scheduling multiprocessor system node operand operations optimal output packet parallel computation parallel processing performance Petri pipeline port problem Proc processing elements processor programming languages queue reconfiguration scheduling scheduling algorithms sequence sequential simulation static storage structure subgoals subnetwork supercomputer sync synchronization systolic array task throughput tion transition transitive closure units variable vector vector processing VHSIC VLSI