What people are saying - Write a review
We haven't found any reviews in the usual places.
Interconnect 1000 am 1200
S2 3S Thermal Aware CellBased FullChip Electromigration Reliability Analysis
S2 4S Accounting for the Skin Effect during Repeater Insertion
41 other sections not shown
algorithm and/or a fee applied architecture ATPG Bayesian network benchmark block Boolean buffer cache capacitance chip circuit CMOS computation Computer-Aided Design constraints Copyright 2005 ACM cycles delay digital or hard efficient flip-flop FPGA frequency gate graph IEEE implementation increase input Integrated Circuits interconnect iteration jitter layout leakage power load logic loop memory method mode modules MOSFET node noise operation optimization output paper path performance personal or classroom phase PIM Lite PLBs post on servers POWER4 prior specific permission problem Proc processor proposed redistribute to lists reduce reordering requires prior specific routing runtime S-Boxes scheme Section shown in Figure shows signal simulated annealing simulation specific permission and/or SRT tasks structure subcircuits substrate substrate coupling subthreshold leakage switching synchronization Table technique throughput tile transistor transition fault variables vector VHDL VLIW VLSI voltage width wire