General Theory Relating to the Implementation of Concurrent Symbolic Computation
University of Cambridge, Computer Laboratory, 1989 - Computer architecture - 113 pages
Abstract: "The central result of this work is the discovery of a new class of architectures, which I call D-RISC, sharing some characterisctics of both data flow and von Neumann RISC computers, for concurrent computation. This rests on an original and simple theory which relates the demands of concurrent computation on hardware resources to the fundamental performance constraints of technology. I show that dataflow and von Neumann architecture have different fundamental hardware constraints to performance, and that therefore a D-RISC architecture, which balances these two constraints, is likely to be optimum for concurrent computation. The work forms four related section
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allocation ALU operation analysis asynchronous bandwidth bandwidth limited computation block bus latency cache hit rates cache miss Chapter cloning communication compiled concurrent computation considered constraints corresponding cost CPU design created critical path D-RISC D-RISC design data access dataflow CPUs dataflow machines datum dynamic efficient Elaa example export computation frame cache functional languages garbage collection global name graph hardware heap increase instruction inter-thread intermediate data latency and bandwidth latency limited computation lazy evaluation localise locations mapping memory mergesort multiple thread multiprocessor multiprocessor system Neumann NFIB node number of threads operand optimisation overhead pipeline pointer prefetch processor reference count requires resource reuse RISC scheduling Section semantics sequencer sequential single thread stack frames static strategy structure symbolic computation Symbolic Procedure synchronisation synchronous tail recursion test programs thread computation thread creation thread reference thread switching thread's value tree uniprocessor update vectors waiting