Handbook of FPGA Design Security
Springer Science & Business Media, Jun 18, 2010 - Technology & Engineering - 177 pages
The purpose of this book is to provide a practical approach to managing security in FPGA designs for researchers and practitioners in the electronic design automation (EDA) and FPGA communities, including corporations, industrial and government research labs, and academics. This book combines theoretical underpinnings with a practical design approach and worked examples for combating real world threats. To address the spectrum of lifecycle and operational threats against FPGA systems, a holistic view of FPGA security is presented, from formal top level speci?cation to low level policy enforcement mechanisms, which integrates recent advances in the ?elds of computer security theory, languages, compilers, and hardware. The net effect is a diverse set of static and runtime techniques that, working in coope- tion, facilitate the composition of robust, dependable, and trustworthy systems using commodity components. We wish to acknowledge the many people who helped us ensure the success of ourworkonrecon?gurablehardwaresecurity.Inparticular,wewishtothankAndrei Paun and Jason Smith of Louisiana Tech University for providing us with a Lin- compatible version of Grail+. We also wish to thank those who gave us comments on drafts of this book, including Marco Platzner of the University of Paderborn, and Ali Irturk and Jason Oberg of the University of California, San Diego. This research was funded in part by National Science Foundation Grant CNS-0524771 and NSF Career Grant CCF-0448654.
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High Assurance Software Lessons and Techniques
Hardware Security Challenges
FPGA Updates and Programmability
Memory Protection on FPGAs
Spatial Separation with Moats
A Design Example
Appendix A Computer Architecture Fundamentals
Other editions - View all
access control access policy AES core algorithm application ASICs bitstream cache chip circuit CLBs Common Criteria compartment compiler complexity components Computer Security configuration covert channel CPUs crypto cryptographic cycle data remanence decryption design flow Design Tip detection device drawbridges embedded system ensure evaluation example formal formal verification FPGA FPGA design functions gate hard-wired hash higher-level Huffmire IEEE implementation input integrity interconnect interface isolation kernel language logic malicious hardware memory access memory protection MicroBlaze moats module Module2 multiple off-chip memory on-chip partial reconfiguration partition performance privilege problem Proceedings range Range2 Reconfigurable computing reconfigurable hardware reference monitor regular expression requires routing security policy segments shared side channel side channel attacks simulation specification Springer Science+Business Media SRAM subversion switchbox Symposium techniques testing trusted trustworthy verification Verilog Xilinx