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DEPENDABILITY MODELING AND EVALUATION
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algorithm applied arbiter architecture assumed binary tree built-in self-test bus master Byzantine Agreement checker chip cluster completion components computing systems concurrent retry scheme considered correct processes DCVS block DCVS circuit dependability design faults diameter duplex system error detection evaluation execution fault coverage fault detection fault-free fault-secure Fault-Tolerant Computing faulty cell faulty processes feedback vertex set Figure flip-flops functional circuit graph H-tree Hamilton cycle Hamilton path hardware fault heuristic hypercube hypertree IEEE IEEE Trans implementation input interconnection logic machine Markov Markov chain messages method multiprocessor networks node obtained operation optimal output parallel computing parameters PE's performed phase problem Proc processing modules processor proposed quorum disk reconfiguration redundancy reliability rollback scheme scan self-testing Sender shown signature structure stuck-on faults subtree Symp systolic arrays Table task technique test patterns testability transition tree grammar variants VAXcluster VAXcluster system VLSI yield