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Memory Latency and Synchronization
Dataflow Simulation Studies
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algorithm Annual Symp Appendix branch penalties branch prediction branch-target calli M[cP cessor cmppt column comparison routines compiler Computer Architecture concurrent threads context switch cycles cycles/transfer dataflow coprocessor Dataflow Languages Daxpy iteration Decode Execute Writeback delayed branch dynamically-scheduled superscalar processor Eqntott FIFO Figure floating-point Fortran hide memory latency hybrid architecture i+3 th instruction IEEE indirect branch instruction i+2 instruction i+3 th Intel's i860 microprocessor latency and synchronization linking threads Linpack matrix multiplication multiprocessor system Object-based Languages object-oriented object-oriented programming operand optimum utilization performance degradation pfadd pfld fld pfmul pfadd pfld pipelined architecture Pipelined Processors prefetch unit private memory Proc procedural interfaces procedure-level granularity remote procedure call RISC and Superscalar secondary cache sequential instruction shared-memory simulations single-pipeline sort algorithm speedup store Rl M[cP Superpipelined superscalar architectures Superscalar Multiprocessors synchronization points synchronization variable Table th instruction i+3 trace scheduling vector length vector routine VLIW