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Memory Latency and Synchronization
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Appendix bitonic-merge sort branch penalties branch prediction branch-target cmppt column comparison routines compiler Computer Architecture concurrent threads context switch CPIpenalty CPIsimulated cycles cycles/transfer dataflow coprocessor Dataflow Languages Daxpy iteration Decode Execute Writeback delayed branch dynamically-scheduled superscalar processor Eqntott Fetch Decode Execute FIFO Figure floating-point Fortran fst pfmul hide memory latency hybrid architecture i-1 th instruction i-H2 th IEEE indirect branch instruction instruction instruction Intel's i860 microprocessor latency and synchronization Linpack matrix multiplication memory location multiprocessor system Object-based Languages object-oriented object-oriented programming บบ operand optimum utilization performance degradation pfadd pfadd pfld pfmul pfadd pipelined architecture Pipelined Processors prefetch unit private memory procedural interfaces procedure-level granularity remote procedure call RISC and Superscalar secondary cache sequential instruction shared-memory simulations single-pipeline sort algorithm speedup store R1 McP Superpipelined superscalar architecture Superscalar Multiprocessors synchronization points synchronization variable Table th i th trace scheduling vector length vector routine VLIW