High Performance Computing: 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings
Alex Veidenbaum, Kazuki Joe, Hideharu Amano, Hideo Aiso
Springer, Dec 5, 2003 - High performance computing - 566 pages
This book constitutes the refereed proceedings of the 5th International Symposium on High-Performance Computing, ISHPC 2003, held in Tokyo-Odaiba, Japan in October 2003. The 23 revised full papers and 16 short papers presented together with 4 invited papers and 7 refereed papers accepted for a concurrently held workshop on OpenMP (WOMPEI 2003) were carefully reviewed and selected from 58 submissions. The papers are organized in topical sections on architecture, software, applications, and ITBL.
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High Performance Computing Trends
Overview of an Adaptive Multithreaded Architecture
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algorithm allocation analysis application architecture array auto-tuning bandwidth benchmark beneficial area Berlin Heidelberg 2003 block branch predictor cache misses ccNUMA Cilk circulant graphs clathrate cluster compiler compression configuration Cook's Theorem cycles data layout dimer disk distributed dynamic Earth Simulator environment Ethernet evaluation execution fetch Figure Fortran function graph grid hardware hyper-threading IEEE implementation improved instructions interface ISHPC ITBL Japan latency LNCS load loop matrix matrix multiplication mechanism memory method module multiple multithreaded node NP-complete OpenMP operations optimization packet parallel computers parameters performance ports problem Proc processors proposed queue reduce runtime scalability scheduling SDSM server shared shows simulation Simultaneous Multithreaded speedup strand structure supercomputer synchronization task technique throughput tile topology vector vector processors Veidenbaum visualization VPN router workloads