High Performance Datacenter Networks: Architectures, Algorithms, and Opportunities
Datacenter networks provide the communication substrate for large parallel computer systems that form the ecosystem for high performance computing (HPC) systems and modern Internet applications. The design of new datacenter networks is motivated by an array of applications ranging from communication intensive climatology, complex material simulations and molecular dynamics to such Internet applications as Web search, language translation, collaborative Internet applications, streaming video and voice-over-IP. For both Supercomputing and Cloud Computing the network enables distributed applications to communicate and interoperate in an orchestrated and efficient way. This book describes the design and engineering tradeoffs of datacenter networks. It describes interconnection networks from topology and network architecture to routing algorithms, and presents opportunities for taking advantage of the emerging technology trends that are influencing router microarchitecture. With the emergence of "many-core" processor chips, it is evident that we will also need "many-port" routing chips to provide a bandwidth-rich network to avoid the performance limiting effects of Amdahl's Law. We provide an overview of conventional topologies and their routing algorithms and show how technology, signaling rates and cost-effective optics are motivating new network topologies that scale up to millions of hosts. The book also provides detailed case studies of two high performance parallel computer systems and their networks. Table of Contents: Introduction / Background / Topology Basics / High-Radix Topologies / Routing / Scalable Switch Microarchitecture / System Packaging / Case Studies / Closing Remarks
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adaptive routing adversarial traffic patterns applications arbitration bandwidth BlackWidow block diagram cables chapter chip Clos Clos network cloud computing connected conventional butterfly cost Cray Inc Cray XT crossbar crossbar switch datacenter deadlock described destination deterministic routing dimension dragonfly topology Ethernet example exploit flattened butterfly flit flow control folded-Clos topology Gb/s global channel hierarchical high-performance high-radix routers high-radix topologies hop count hypercube HyperX implemented indirect network input buffer input port interconnection network interface intermediate node latency load-balancing low-radix memory mesh microarchitecture minimal routing multiprocessor network links non-minimal routing offered load optical output arbiter output port packaging constraints parallel computer path diversity performance phit pin bandwidth processing nodes processor provides queue rack radix router microarchitecture routing algorithm routing decision scalable scale SeaStar router SerDes server shown in Figure signaling subswitch supercomputer switch allocation throughput torus torus network traverse UGAL VC allocation virtual channel wire YARC router