High Performance Embedded Architectures and Compilers: Fourth International Conference, HiPEAC 2009

Front Cover
André Seznec
Springer Science & Business Media, 2009 - Computers - 420 pages
0 Reviews

This book constitutes the refereed proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January  2009.

The 27 revised full papers presented together with 2 invited keynote paper were carefully reviewed and selected from 97 submissions. The papers are organized in topical sections on dynamic translation and optimisation, low level scheduling, parallelism and resource control, communication, mapping for CMPs, power, cache issues as well as parallel embedded applications.

 

What people are saying - Write a review

We haven't found any reviews in the usual places.

Contents

Improving Transactional Memory Performance through Dynamic Transaction Reordering
4
Predictive Runtime Code Scheduling for Heterogeneous Architectures
19
Collective Optimization
34
High Speed CPU Simulation Using LTU Dynamic Binary Translation
50
Integrated Modulo Scheduling for Clustered VLIW Architectures
65
Software Pipelining in Nested Loops with PrologEpilog Merging
80
A Flexible Code Compression Scheme Using Partitioned LookUp Tables
95
MLPAware Runahead Threads in a Simultaneous Multithreading Processor
110
Adapting Application Mapping to Systematic WithinDie Process Variations on Chip Multiprocessors
231
Accomodating Diversity in CMPs with Heterogeneous Frequencies
248
A Framework for Task Scheduling and Memory Partitioning for MultiProcessor SystemonChip
263
Hybrid SuperSubthreshold Design of a Low Power ScalableThroughput FFT Architecture
278
Predictive Thermal Management for Chip Multiprocessors Using Codesigned Virtual Machines
293
Hybrid Dataflow Graph Execution in the Issue Logic
308
Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures
324
Revisiting Cache Block Superloading
339

IPC Control for Multiple RealTime Threads on an InOrder SMT Processor
125
A Hardware Task Scheduler for Embedded Video Processing
140
Finding Stress Patterns in Microprocessor Workloads
153
Deriving Efficient Data Movement from Decoupled AccessExecute Specifications
168
MPSoC Design Using ApplicationSpecific Architecturally Visible Communication
183
Communication Based Proactive Link Power Management
198
Mapping and Synchronizing Streaming Applications on Cell Processors
216
An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
355
InNetwork Caching for Chip Multiprocessors
373
Parallel LDPC Decoding on the CellBE Processor
389
Parallel H264 Decoding on an Embedded Multicore Processor
404
Author Index
419
Copyright

Other editions - View all

Common terms and phrases