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TECHIOLOGY BASE FOB VLSIDSP
Binary Connectives of Two Variables
Solution of Poissons Equation for 400 KeV Implant
16 other sections not shown
allows applications architecture arithmetic bit-serial bitlines block floating point butterfly operations capacitance carry-propagate adder carry-save adder cathode cell Chapter circuit circuitry clock cycles CMOS CMOS process coefficients computation Control Sequencer CUSP chip CUSRAM CUSTIM decoder delay devices diode logic discussed drivers dual rail adders flip-flop floating point full adder function hardware high performance host implant implemented input interconnect latched megabit memory mode MOSFET MSFF n-devices NAND PLA NMOS on-chip parallel multiplier parity photomicrograph pipelined plane point FFT power dissipation Precharge Prime Factor Algorithm problem processor product term Programmable Logic Arrays propagation Pt-Si pulldown pullup radix-4 butterfly reduced Reusens RSRs scaling control scan Schottky diode SCMOS PLAs serial multipliers series resistance shift registers shown in Figure signal processing simulated speed SROM static switching systolic array throughput tion transistor transmission gate logic VLSI voltage watchdog wordline worst XROM