I860 64-bit Microprocessor Hardware Reference Manual |
Common terms and phrases
1860 microprocessor 1UF 1UF 64-Bit Microprocessor active address bus asserted big endian bits boundary scan boundary scan mode BREQ BSCN bus contention bus cycle byte enable capacitor characteristic impedance chip select circuit clock cycle column address data bus data cache deasserted decode delay dirbase DRAM DRAM controller endian EPROM execution external floating-point unit FRAME BUFFER function goto CIDLE graphics HOLDA I/O devices impedance input instruction cache IOWR LADS latched load Memory Cycle memory subsystem MULTIBUS NENE NON-PIPELINED NRDY operands output outstanding cycles page table parallel parity performance pipelined pixel power dissipation processor provides RASn read cycle REFREQ refresh RESET row address sampled serial shift mode shown in Figure SRAM st.b state_diagram termination transfer transmission line TRFQn valid VRAM wait-states write cycle write data write operations