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A MOdular and Reprogrammable
Teramac Configurable Custom Computing
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adder algorithm application architecture bitvoctor block buffer cell CHAMP2 circuit circuitry CLBs Clock Enable compiler components configuration connected convolution coprocessor crossbar Custom Computing Machines custom-instruction Dalsa debugging described developed device DISC downto Enable++ execution Field Programmable floating point FPGA FPGA chips FPGA-based systems FPGAs for Custom function Gate Arrays global hardware description language Hidden Markov Models host IEEE image processing implementation input instruction modules interface loop memory microprocessor MORRPH board multiplier netlist operand operation output Pamette parallel partitioning performance pins pipeline pixel place and route Plibs port priority queue processor PROTEUS chips prototyping real-time routability RRANN2 Ruby sequencing shown in Figure signal simulation SPARCstation speed Splash stage systolic systolic array Teramac tion TURBOchannel variable Verilog VHDL VLSI voxel Workshop on FPGAs workstation WRLC Xilinx