What people are saying - Write a review
We haven't found any reviews in the usual places.
Ten Lessons for Long Life
ControlTheoretic Techniques and ThermalRC Modeling for Accurate
EnergyEfficient Processor Design Using Multiple Clock Domains with Dynamic
26 other sections not shown
Other editions - View all
algorithm allocation applications apsi average bandwidth bank behavior benchmarks branch execution branch instruction branch prediction buffer bytes bzip2 cache line cache misses clock compiler Computer Architecture configuration counter cycles d-cache data cache delinquent loads dependent disk DRAM dynamic resizing energy consumption energy-delay evaluate Figure fine-grain priority scheduling fixup frequency garbage gzip hardware heap IEEE impact implementation improve in-order issue Itanium iteration L2 cache latency loop memory accesses memory latency Microarchitecture microprocessor minicache Minkachc misprediction miss-rate multithreading node non-vital loads operand optimization overall parallel partitioning performance pipeline pointer prefetching Proceedings processor protocol pthreads Rambus reduce register file request reuse vectors scheme Section selective-sets selective-ways server set-associativity shows simulation simultaneous multithreading spawning speculative execution Speculative Multithreaded squashes static resizing sub-blocks superscalar Symposium on Computer synchronization Table techniques thermal thread-level parallelism tion update value prediction value-speculation voltage workload