IEEE Standard[s], Issue 1596
IEEE, IEEE Computer Society. Microprocessor and Microcomputer Standards Committee, Institute of Electrical and Electronics Engineers, IEEE Standards Board
Institute of Electrical and Electronics Engineers, 1992
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16-byte-aligned address-offset annex autorefresh bandwidth BASED ON SCI bridge broadcast buses bytes of data cache circuitry clock clockRefln clockValue cmds command components controller is expected CSR Architecture cycles data bytes data-block delay DRAM event packets field specifies flag HIGH-BANDWIDTH MEMORY INTERFACE I/O devices IEEE STANDARD IEEE Std illustrated in figure initial input JTAG memory controller most-significant narrowcast ninth bit node optional oReqHi output packet format parity parity bit performed processing processor quadlet queue RAM9 RamLink interface RamLink slaves refresh operations refreshNow refreshNow3 event request packet response packet retry packet returned ringlet RingLink signaling scheduling SCI SIGNALING TECHNOLOGY selectln selfrefresh shutDown recovery signaling layer SIGNALING TECHNOLOGY RAMLINK slaveld value sourceld STANDARD FOR HIGH-BANDWIDTH status Status Register strobe subaction entries sync packets synchronize SyncLink SyncLink signaling tick-pair tld values topologies typically update value specifies vendor-dependent write transactions write64