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The Memory Latency Problem
Runahead Simulation Methodology
Baseline Runahead Experiments
6 other sections not shown
2-bit counters average runahead episode branch misprediction branch prediction cache line conditional branch cycles Data Stream Prefetch decile demand fetch destination register execution GB/s GO benchmark IJPEG benchmark indirect branch initiated runahead episodes instruction cache miss INSTRUCTION miss initiated INSTRUCTION prefetches Instruction Stream Prefetch Instructions into Runahead L1 instruction cache L2 data cache load and store LOAD miss initiated LOAD prefetches main memory bandwidth memory hierarchy miss initiated runahead MPEG NOL2 non-runahead processor normal operation number of prefetches perfect L1 instruction performance PERL benchmark pipeline plot prefetch requests prefetches during INSTRUCTION prefetches during LOAD prefetches during STORE Processor CPI RA_NOCOPY register file right path prefetches runahead instructions runahead mode runahead processor runahead valid bits sequential shown in Figure Stale Values store instructions STORE miss initiated STORE prefetches store-through STREAM benchmark Stream Prefetch Locality Stream Prefetch Utility target address useless prefetches VORTEX benchmark wrong path prefetches