Instruction-Level Parallelism: A Special Issue of The Journal of Supercomputing

Front Cover
B.R. Rau, J.A. Fisher
Springer Science & Business Media, May 31, 1993 - Computers - 282 pages
Instruction-Level Parallelism presents a collection of papers that attempts to capture the most significant work that took place during the 1980s in the area of instruction-level (ILP) parallel processing. The papers in this book discuss both compiler techniques and actual implementation experience on very long instruction word (VLIW) and superscalar architectures.

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This research paper is a collection of several papers that conducted in order to capture all the significant work done on the subject of ILP during the 1970-1990 and the efforts of those advances that are made during the last three decades for the advancement and revival of ILP are also highlighted. Author discussed the compiler techniques and the actual implementation that are used in VLIW and Superscalar architecture..The main theme of this paper round about the Instruction Level Parallelism (ILP) which is a measure of how many of operations of a computer program can be performed simultaneously. The major purpose of the use of ILP is to speed up the processors and use all the computer resources which in typical processors become idle while the execution of one program This research paper provides a deep overview of ILP and its innovations and downfalls over the past 30 years. The author discussed the different stages of ILP and its working in five major parts .In the first part of section one, the working of ILP execution is described. ILP uses RISC-style operation technique and is a measure of how many operations of a computer program can be performed simultaneously. It is a potential overlapping technique, which gives its users the benefits of circuit improvement and transparency as compared to other traditional processors.ILP technique is highly used by VLIW and superscalar processors. The working of ILP processors is same as that of RISC machine and the major difference between a machine having ILP and the one without ILP is that there may be more than one hardware present in ILP processors depend upon the amount of ILP used in it .Early history of ILP is being discussed in part two of section one .Initially the term” Parallelism” which we call today ” horizontal microcode” appeared in Turing’s 1946 design. The research study of parallel processing in 1960 was revolving around the ILP used in processors. The execution models of these machines resembled to the way towards the execution of machines which which we called now a days Superscalar computers. IBM 360/90 and CDC-6600 are the examples of machines that provide ILP at machine level and use the same technology that we are using today in Superscalar processors. 1970 was the era of tremendous utilization of Instruction level parallelism and the replacement of Read-only Control store with the writeable memory in order to facilitate the user precisely by giving them a large amount of ILP than the early superscalar processors.These fast machines lessen the restriction of traditional idiosyncratic architecture of processor that were built for a single application.For this purpose, RISC concept was used to present simple clean interface to the compiler. The mid of 1970 was the initialization of new style ILP called VLIW (very large instruction word).VLIW was a natural growth of parallelism,and supposed to be the first ILP technology..
1980 was a time span of startup and underway efforts for the development of compiler techniques with VLIW,and its uses for superscalar machines.The use of RISC concept and ILP became very less in this era and only some commercial and scientific industries used a small amount of ILP in their products,such as ZS-1 which could issue upto two instructions each cycle.
In 1990 mostly designers started to investigate the usage of VLIW in order to get some degree of superscalar capabilities in their machines,and at that time it seemed to be exhibit that upto 1995,all the upcoming CPUs will have some degree of ILP in their architecture.But due to lack of documentation of these projects by the designer these efforts were not captured fo later use. Almost everything was done by these group of designers was relevant to what designers are struggle for today. This paper is also an effort to highlight the efforts of those advances.
In the second phase of this paper, description of ILP architecture, its working and what necessary decisions should be take specially when operations are executed normally or speculatively. ILP


An Introduction to This Special Issue
Guest Editors Introduction
History Overview and Perspective
The Multiflow Trace Scheduling Compiler
Architecture and Implementation
Compiling for the Cydra 5
An Effective Technique for VLIW and Superscalar Compilation
InstructionLevel Experimental Evaluation of the Multiflow TRACE 14300 VLIW Computer
Contributing Authors

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