Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings
Vassilis Paliouras, Johan Vounckx, Diederik Verkest
Springer, Oct 6, 2005 - Computers - 753 pages
This book constitutes the refereed proceedings of the 15th International Workshop on Power and Timing Optimization and Simulation, PATMOS 2005, held in Leuven, Belgium in September 2005. The 74 revised full papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-power processors, code optimization for low-power, high-level design, telecommunications and signal processing, low-power circuits, system-on-chip design, busses and interconnections, modeling, design automation, low-power techniques, memory and register files, applications, digital circuits, and analog and physical design.
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Low Power Techniques Applied to a 80C51 Microcontroller
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adder analysis AODV application approach architecture asynchronous average benchmarks Berlin Heidelberg 2005 blocks capacitance cell channel chip circuit clock frequency clock signal cluster CMOS coefficients Computer configuration constraints core critical path cycle decoder delay dynamic voltage scaling efficiency embedded systems energy consumption estimation evaluation execution Figure filter FPGA function gate IEEE implementation increase input instructions integrated interconnect iteration leakage power linear logic loop loop transformations low power low-power memory hierarchy method methodology microcontroller microprocessor minimize minimum mode nodes OFDM operation optimization output overhead Paliouras PAPR PATMOS performance power consumption power dissipation power reduction power supply Proc processor proposed algorithm reduce ripple-carry adder scan chain scheduling Section signal simulation SRAM static supply voltage switching activity Table techniques temperature threshold voltage tion transistor transition Verilog Verkest Eds VLSI voltage scaling points Vounckx wire