Intelligent Memory Systems: Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000. Revised Papers

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Springer Science & Business Media, Aug 29, 2001 - Computers - 191 pages
We are pleased to present this collection of papers from the Second Workshop on Intelligent Memory Systems. Increasing die densities and inter chip communication costs continue to fuel interest in intelligent memory systems. Since the First Workshop on Mixing Logic and DRAM in 1997, technologies and systems for computation in memory have developed quickly. The focus of this workshop was to bring together researchers from academia and industry to discuss recent progress and future goals. The program committee selected 8 papers and 6 poster session abstracts from 29 submissions for inclusion in the workshop. Four to five members of the program committee reviewed each submission and their reviews were used to numerically rank them and guide the selection process. We believe that the resulting program is of the highest quality and interest possible. The selected papers cover a wide range of research topics such as circuit technology, processor and memory system architecture, compilers, operating systems, and applications. They also present a mix of mature projects, work in progress, and new research ideas. The workshop also included two invited talks. Dr. Subramanian Iyer (IBM Microelectronics) provided an overview of embedded memory technology and its potential. Dr. Mark Snir (IBM Research) presented the Blue Gene, an aggressive supercomputer system based on intelligent memory technology.
 

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Contents

A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro
1
Software Controlled Reconfigurable OnChip Memory for High Performance Computing
15
Initial Results
33
Memory System Support for Dynamic Cache Line Assembly
56
Adaptively Mapping Code in an Intelligent Memory Architecture
71
The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems
85
Memory Management in a PIMBased Architecture
104
Exploiting OnChip Memory Bandwidth in the VIRAM Compiler
122
Aggressive MemoryAware Compilation
147
EnergyPerformance Design of Memory Hierarchies for ProcessorinMemory Chips
152
A New Analysis and Optimization System for FlexRAM Architecture
160
PerformanceEnergy Efficiency of Variable LineSize Caches for Intelligent Memory Systems
169
Accelerating Architecture Studies for PIMBased Systems
179
CompilerDirected Cache Line Size Adaptivity
183
Summary of QuestionAnswer Sessions for Workshop Presentations
188
Author Index
192

A Framework for Flexible Compiler Generated Data Caching
135

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