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MultiProcessor Developments in the United States
Triggers for LEP Experiments
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ACP system ALEPH algorithms allows application architecture array Branchbus buffer calorimeter CAMAC cells cellular automata CERN channels chip circuit collider communication components connected cycle data acquisition system data cable data flow DELPHI detector developed devices drift chambers dual-port Event Builder event rate event reconstruction experiments fast FASTBUS Fermilab filter floating point FORTRAN front end front-end electronics hadronic hardware High Energy Physics host IEEE implemented INFN input interconnection interface kbytes lattice level trigger Level-2 logic machine Mbyte memory Micro VAX microprocessors MicroVAX module multiple multiprocessor multiprocessor system muon nodes on-line OPAL operation output parallel particle performance pipeline Polyp processing protocol readout running segment signals simulation speed standard Switch tape track finding transfer transputer trigger decision trigger processor trigger system VAXELN VME crates VMEbus ZEUS