Logic Design for Array-Based Circuits: A Structured Design Methodology
This book will show you how to approach the design covering everything from the circuit specification to the final design acceptance, including what support you can expect, sizing, timing analysis, power and packaging, various simulations, design verification, and design submission.
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AC POWER COMPUTATION
CHAPTER 8 SIMULATION
CHAPTER 9 FAULTS AND FAULT DETECTION
1 MUX D FLIPFLOP CIRCUIT
CHAPTER 10 DESIGN SUBMISSION
GLOSSARY OF TERMS
CASE STUDY PREVENTING HOLD VIOLATIONS DUE TO CLOCK SKEW
CHAPTER 7 POWER CONSIDERATIONS
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AC power AC test allow AMCC AMCCERC AMCCSUBMIT annotation array series array vendor ASIC at-speed simulation Back-Annotation BiCMOS arrays bidirectional macros bipolar arrays bit-slice capacitance circuit clock path CMOS Darlington DC power deﬁned Design Manual design submission drive ECL 10K ECL input ECL output equation equivalent gates estimate external set-up falling edge fan-in fan-out load fault fault coverage Figure ﬁle ﬁnal ﬁrst ﬁxed ﬂip/ﬂop frequency Front-Annotation functional simulation gate tree I/O cells IEVCC interconnect interface cell interface macros internal macros junction temperature k-factors layout loading delays logic macro library metal minimum netlist output macros overhead current parametric path propagation delay performed place and route placement power and ground power dissipation power supply propagation delay reset schematic schematic capture set-up and hold speciﬁc speed switching TABLE test vectors thermal diode toggle vector set veriﬁers Verilog voltage wire-OR workstation worst-case maximum worst-case multipliers