Low-Power Design of Nanometer FPGAs: Architecture and EDA
Low-Power Design of Nanometer FPGAs Architecture and EDA is an invaluable reference for researchers and practicing engineers concerned with power-efficient, FPGA design. State-of-the-art power reduction techniques for FPGAs will be described and compared. These techniques can be applied at the circuit, architecture, and electronic design automation levels to describe both the dynamic and leakage power sources and enable strategies for codesign.
What people are saying - Write a review
We haven't found any reviews in the usual places.
Chapter 2 Power Dissipation in Modern FPGAs
Chapter 3 Power Estimation in FPGAs
Chapter 4 Dynamic Power Reduction Techniques in FPGAs
Chapter 5 Leakage Power Reduction in FPGAs Using MTCMOS Techniques
Other editions - View all
Actel activity profiles activity region activity vectors ASIC AT-VPack benchmarks calculated capacitance circuit clock CMOS CMOS devices connected cost function critical path cycles data hazard delay elements Design Automation Conference dual-VDD dynamic power dissipation EMap evaluated fanout Field Programmable Gate FIGURE flip-flop insertion FPA algorithm FPGA architecture FPGA fabric FPGA power glitching power Hamming distance Hence increase input vector leakage power dissipation leakage power savings leakage savings logic blocks logic clusters logic resources maxCap minimize Moreover MTCMOS multiplexer Najm Nanometer netlist node number of inputs output P-block packing algorithm pass-transistor phase pin reordering placement power model power reduction power-aware Programmable Gate Arrays pseudocode R-LAP routing resources shown in Fig signal probabilities simulation sleep region sleep transistor spatial correlation SRAM subthreshold leakage subthreshold leakage current switching activity T-MTCMOS technology mapping tion topological sorting transition density VDDH VDDL VLSI voltage Xilinx