Microprocessor-based parallel architecture: for reliable digital signal processing systems
This book presents a distributed multiprocessor architecture that is faster, more versatile, and more reliable than traditional single-processor architectures. It also describes a simulation technique that provides a highly accurate means for building a prototype system in software. The system prototype is studied and analyzed using such DSP applications as digital filtering and fast Fourier transforms. The code is included as well, which allows others to build software prototypes for their own research systems.The design presented in Microprocessor-Based Parallel Architecture for Reliable Digital Signal Processing Systems introduces the concept of a dual-mode architecture that allows users a dynamic choice between either a conventional or fault-tolerant system as application requirements dictate. This volume is a "must have" for all professionals in digital signal processing, parallel and distributed computer architecture, and fault-tolerant computing.
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Microprocessor-Based Parallel Architecture for Reliable Digital Signal ...
Alan D. George
Limited preview - 2018
Microprocessor-based Parallel Architecture: For Reliable Digital Signal ...
Alan D. George,Lois Wright Hawkes
No preview available - 2018
access move 1,n0 access move N/2),n0 architecture bit-rev access move bit-reverse access move buffer space clock coeff computer system continue infinite loop data propagation data ptr register dc dc dc device digital filter Digital Signal Processing equates & macros failure fast Fourier transformations fault fault-tolerant system floating-point FT mode imag parts nop implementation incl operating system include OP_SYS.lNC init_PE initialize input data initialize output data input data ptr input values instruction restrictions interface jmp LP linear access move linear array memory microprocessors MIMD move buff,r0 mpfft multiprocessor N-pt FFT pass nodes non-FT mode normal output ordering offset inc associated opcode operating system equates output data ptr parallel computing PE-to-PE perform N-pt FFT port previous input/PE pts imag pts real put_PE real-time computing real-time DSP register do N,lp1 reliability set aside buffer SIMD simulation stage PEs systolic array techniques tion transfer voter