Microprocessor-Based Parallel Architecture for Reliable Digital Signal Processing Systems
This book presents a distributed multiprocessor architecture that is faster, more versatile, and more reliable than traditional single-processor architectures. It also describes a simulation technique that provides a highly accurate means for building a prototype system in software. The system prototype is studied and analyzed using such DSP applications as digital filtering and fast Fourier transforms. The code is included as well, which allows others to build software prototypes for their own research systems.
The design presented in Microprocessor-Based Parallel Architecture for Reliable Digital Signal Processing Systems introduces the concept of a dual-mode architecture that allows users a dynamic choice between either a conventional or fault-tolerant system as application requirements dictate. This volume is a "must have" for all professionals in digital signal processing, parallel and distributed computer architecture, and fault-tolerant computing.
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Microprocessor-Based Parallel Architecture for Reliable Digital Signal ...
Alan D. George
Limited preview - 2018
Microprocessor-based Parallel Architecture: For Reliable Digital Signal ...
Alan D. George,Lois Wright Hawkes
No preview available - 2018
architecture bit-rev access fftoat bit-reverse access buffer space clock coeff communication computer system continue infinite loop D0 instruction restrictions data propagation data ptſ register delayed data element device digital filter Digital Signal Processing ds Org init_PE equates & macros failure fast Fourier transformations fault fault-tolerant system floating-point FT mode implementation incl Operating system init initialize input data initialize output data input data ptſ input values JMP STOP linear acceSS 1,nO linear array memory microprocessors MIMD move do nop move move move mpfft mpfft multiprocessor N-pt FFT pass N,fftoat,ROM TBL,ROM nodes non-FT mode NOPs for D0 normal output ordering Offset inc associated opcode Operating system equates output data ptſ output results parallel computing PE-to-PE perform N-pt FFT port previous input/PE processors pts imag pts real real-time computing real-time DSP reliability set aside buffer SIMD simulation stage PEs SYS.INC techniques tion transfer voter