Microprocessor systems design, Volume 1
Microprocessor systems design: an overview; Information devices; Information storage devices; Coding and MSI building blocks; A central processor unit instruction set; An LSI central processor unit; The memory subsystem; The I/O subsystem; Languages and language translation; Addressing structures; I/O structures and techniques; Interrupt structures; Direct memory access: structures and techniques; Microprocessor architectural themes; Appendices; Bibliography; Index.
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Analog Building Block to Digital Building Block Transformations
Purely Digital Building Blocks 36 Interfamily Interface Blocks
Memory Circuits 48 Counters 52 Shift Registers
18 other sections not shown
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accumulator active LOW address bus algorithm allows basic binary number buffer building blocks byte cell channel chapter circuit circuitry clock pulse command contents control lines COSMAC data bus data pointer decoder delay diagram direct addressing disabled Figure flag flip-flop function gate hardware implemented index register input port integrated circuits Intel interface interrupt request interrupt structure interrupt system Intersil JUMP loaded logic loop machine MACRO memory microprocessor mode MOSFET MOSTEK multiplexer normally nsec occurs opcode operation output port pointer priority processor program counter RAM address latch register file request line reset SC/MP sequence serial service routine shift register shown in Fig signal Signetics 2650 specified stack status bits storage stored Strobe subroutine subsystem symbol SYNC teletype tion transfer transition tri-state UART utilizes vector voltage word WRITE zero