Microprogrammable Parallel Computer: MUNAP and Its Applications
This book takes up the challenge offered by recent advances in theoretical computer science and artificial intelligence that have created a demand for a radically different type of computer architecture. It demonstrates the possibility of register transfer level parallel computing with microprogrammable flexible architecture that can fulfill a wide variety of user requirements, and provides all the necessary technical information to understand the process of design, development, and evaluation of this innovative MUNAP computer.After introducing the basic concepts in the computer architecture and microprogramming area, the book describes how the architect goes about selecting microoperations, considering software/firmware/hardware tradeoffs and what schemes might be used for interleaved memory access and interconnection network. Microprogrammed computer models are defined for the evaluation of computers with similar architectures.Microprogrammable Parallel Computer presents the results of exhaustive experimentations with this architecture showing how it can be exploited in current research on emulation of a machine language, tagged architectures, language processing for Smalltalk-80 and Prolog, software testing, database systems, 3D graphics, and numerical computation.Contents: Introduction. Design Principle. Basic Organization. Preliminary Evaluation. Hardware Development. Firmware Development. Applications. Architectural Evaluation and Improvement. Future Directions.Takanobu Baba is an Associate Professor, Department of Information Science, Utsunomiya University, Japan. Microprogrammable Parallel Computer is included in the Computer Systems Series, edited by Herb Schwetman.
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activate nanoprograms application architectural features average number basic bit count microprogram byte code clause computer architecture concatenation control memory D-BUS data flow data structure data transfer data types database debugging decoding defined described developed ECL IPSE effect emulation Evaluation example execution steps field firmware flags four PUs functional control hardware I-code implementation input interaction interface interpreter level parallelism logic LU decomposition machine cycles main memory method micro level microassembler microinstruction microsteps MIMD MNFL modules MSDL multiple MUNAP nano instructions nanoaddress nanolevel nanoprocesses nanoprogram nanoprogram memory object optimization parallel processing performance phase pointer port registers primitive problem Prolog ratio register transfer level requires sequence serial operation shift shown in figure shuffle exchange network SIMD software testing sparse matrix specified SPMO stack statements Table tagged architecture utilization variables word