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Cache parameters and memory power consumption of video algorithms 331 104
a review 331 106
Parallelism analysis of the memory systems in singlechip VLIW video signal processors
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algorithms audio bitrate bitstream bitstream parsing C*RAM cache block chip code words coefficients compiler computation core cycle data address data paths Discrete Cosine Transform DRAM elements encoder execution external memory Figure fractal compression fractal image compression functional units hardware IDCT IEEE image compression implementation input instruction address instruction scheduler instruction set interface inverse quantization issue-slot load localized domain-pools long instruction word loop macroblocks matrix-memory media processor memory power consumption memory units MIMD modules motion compensation motion estimation motion vector MPEG multimedia multimedia applications number of bits on-chip operands optimized output parallel PE's performance pixels prefetch requests prefetch table processor arrays programmable PSNR quantization reduced register file requires RISC scheme ShowBits Signal Processing SIMD simulation SRAM standard stream prefetch instruction Super Operations synchronization on data tasks transform TriMedia video applications video processing VLIW VLIW architectures