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The CDC CYBER170
The Honeywell Series 60 Level 66
7 other sections not shown
activity address structure algorithms bits Burroughs bytes C.mmp cache invalidate called Carnegie-Mellon University central processor cessor cluster Computer Architecture Computer Systems connection scheme contains corresponding crossbar switch Data Channels described descriptor list Digital Equipment Corp discussed DMap error recovery execution failure Fault-Tolerant feature Figure functions hardware Honeywell Hydra I/O device I/O operation I/O requests implementation instruction interprocessor communication interprocessor interrupt interrupt handling routine interrupt vector kernel mode Kmap main memory mapping mechanism Medusa memory addresses memory interference memory modules models MP configuration MP system multipro multiprocessor systems number of processors operating system page table Parallel Processing performance physical address physical memory present problems queue reconfiguration reentrant registers reliability requestor scheduling shared memory SIGP Slocal specific stack storage symmetric synchronisation Systems Proceedings tasks techniques Unibus uniprocessor Univac user mode user programs