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STATE INITIALIZATION AND STATE VERIFICATION
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achieve state controllability adjacency matrix algorithm arbitrarily initialized Boolean difference branch insertion column combinational module complete test Comput corresponding coupled deleting disjoint paths dual equation exists external connection extra input fault coverage fault diagnosis fault distinguishable fault locatability faults associated full adder functional dominance functionally integrated hardware cost id(v IEEE IEEE Trans incoming branch initialization sequence input pattern input sequence input space insert a branch ip(v is(v linear linearly independent matrix memory elements mod-2 summing circuit mode control switch modified network digraph non-zero entries non-zero ordered vertices observable od(v outgoing branches output sequence primary input-order pairs primary inputs primary outputs Procedure 3.1 r(Mz rank of B:A sequential circuit sequential logic network sequential machines sequential module sequential network set of outgoing set of paths shift register shown in Figure simulated special test paths synchronous sequential logic test mode Theorem undetectable faults unreachable vertex variables verified