PA-RISC 2.0 Architecture

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Prentice Hall PTR, 1996 - Computers - 496 pages
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Hewlett-Packard's PA-RISC architecture is one of the most mature Reduced Instruction Set Computer designs in the industry. This book is the first publicly available, detailed description of the next revision of the PA-RISC architecture. Covers the RISC characteristics of PA-RISC, PA- RISC processing resources, addressing and access control, control flow, interruptions, and an overview of the instruction set and floating point corprocessor. For system designers and analysts, system software programmers, application developers, and technical managers.

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Processing Resources
Figure 22 General Registers
Figure 28 Control Registers 211

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