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PCI and PCI-X Hardware and Software: Architecture and Design
Edward Solari,George Willse
Limited preview - 2005
32 data 64 data bit add-in card ADDRESS PHASE address space Base Address Base Address Register bit PCI bus BURST access cycle bus cycle bus ownership Bus Speciﬁcation cache controller cache line CLK signal line conﬁguration access cycle connector data bit PCI DATA PHASE deasserted deﬁned device drivers DEVSEL DUAL ADDRESS expansion ROM Fast Back-to-Back ﬁeld Figure ﬁrst FRAME function HDRAM Header HOST bus HOST CPU HOST/PCI BRIDGE I/O address identiﬁes interface interrupt acknowledge cycle Interrupt Pin IRDY LEGACY bus line is asserted lines are driven Lock master Master Abort microprocessor PAR64 signal lines parity error PCI bus master PCI Conﬁguration Manager PCI device PCI resource PDRAM platform Protected Mode protocol pull-up resistors read access cycle Retry termination SDONE signal line shadow RAM signal line period special cycle speciﬁc Status Register System BIOS system resources tennination TRDY tri-stated valid video device write access cycle