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DESCRlPTlONS OF PERlPHERALS
Word or byte processing
9 other sections not shown
Address Register asserted asynchronous Bauds bit is set block BlT NAME Buffer Register bus address bus load bus master byte cabinet cable card reader channel CHECK Circuit cleared by lNlT clock connector Control and Status core memory CSR bit data bits Data Buffer data transfer dataset DATl DECtape DESCRlPTlON Direct Memory Access disk double buffered drive function half-duplex input interface interrupt request jumper LlNE lndicates lnitialize lnput lnterrupt Enable lNTR logic Maintenance memory mode modem module Mounting MSYN multiplexer null modem operation output panel paper tape parity bit peripheral printer processor program control punch RBUF read station read/write READY Received Data REGlSTER RESET selected serial Set to indicate signal silo slave SPEClFlCATlONS speed SSYN Status Register switch System Unit Teletype terminal track transmit UART UNIBUS UNlBUS vector address Word Count write WRlTE