PCI Bus Demystified

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Newnes, May 17, 2004 - Technology & Engineering - 250 pages
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The peripheral component interconnect (PCI) bus is the dominant bus system used to connect the different elements making up today's high-performance computer systems. Different PCI implementations have also been developed for such applications as telecommunications and embedded computing. If an application calls for high speed, high reliability, flexible configuration, and bus mastering, then PCI is the only logical bus choice. This book is an applications-oriented introduction to the PCI bus, with an emphasis on implementing PCI in a variety of computer architectures. Special attention is given to industrial and mission-critical applications of PCI bus.

·Fully describes PCI electrical specifications, mechanical requirements, and signal types
·Covers advanced topics through numerous design examples to increase the readers understanding of the subject
·Includes updated coverage of PCI-X 2.0
 

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Contents

2 Arbitration
15
3 Bus Protocol
23
4 Optional and Advanced Features
41
5 Electrical and Mechanical Issues
51
6 Plug and Play Configuration
77
7 PCI Bridging
101
8 System Configuration and the PCI BIOS
123
9 CompactPCI
137
11 Introduction to PCIX
171
12 PCIX Protocol
175
13 PCIX Configuration and Initialization
199
14 PCIX Electrical and Mechanical Features
217
back matter
235
Connector Pin Assignments
241
Index
245
Copyright

10 Hot Plug and Hot Swap
153

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Page 9 - PERR# Parity error reports a data parity error on all commands except special cycles. SERR# System error reports address parity errors, data parity errors on special cycle commands, or any other system error where the result would be catastrophic. Interface Control FRAME* Cycle frame is driven by the current master to indicate the beginning and duration of an access. TRDY# Target ready indicates the target agent's, (selected device's), ability to complete the current data phase of the transaction....
Page xiii - Used in This Book The book is roughly divided into two parts. The first part, Chapters 2-5, summarizes the J2EE technologies, introduces RUP and the J2EE Developer Roadmap, and briefly describes our sample application.
Page 10 - For reporting data Parity Errors during all PCI transactions except a Special Cycle.
Page 7 - PCI interface requires a minimum of 47 pins for a target-only device and 49 pins for a master.
Page 8 - PCI transactions and is an input to every PCI device. All other PCI signals except RST# and INTA# through INTD# are sampled on the rising edge of CLK.

About the author (2004)

Doug Abbott is a consultant with over thirty years’ experience, specializing in hardware and software for industrial and scientific data acquisition and embedded product applications. Doug is also a popular instructor and seminar leader, who teaches classes in PC technology and real-time programming for University of California Berkeley Extension. He has taught the techniques of real-time programming and multi-tasking operating systems to hundreds of professional engineers.
Doug Abbott is the principal of Intellimetrix, a consulting firm in Silver City, NM, specializing in hardware and software for industrial and scientific data acquisition and embedded product applications. Among his past and pre-sent clients are Agilent Technologies, Tektronix, Sandia National Laboratory and numerous smaller high-tech com-panies in Silicon Valley.

Mr. Abbott has over thirty years experience in various aspects of computer hardware and software design and has been an independent consultant for the past fifteen years. Prior to founding Intellimetrix, he managed software de-velopment for DSP Technology, Inc, a leading supplier of high-speed instrumentation.

Doug is also a popular instructor and seminar leader, who teaches classes in PC technology and real-time program-ming for University of California Berkeley Extension. He has taught the techniques of real-time programming and multi-tasking operating systems to hundreds of professional engineers. These classes can also be customized and made available for on-site presentation.

Mr. Abbott received an MSEE degree from the University of California at Berkeley.

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