PCI Bus Demystified
The peripheral component interconnect (PCI) bus is the dominant bus system used to connect the different elements making up today's high-performance computer systems. Different PCI implementations have also been developed for such applications as telecommunications and embedded computing. If an application calls for high speed, high reliability, flexible configuration, and bus mastering, then PCI is the only logical bus choice. This book is an applications-oriented introduction to the PCI bus, with an emphasis on implementing PCI in a variety of computer architectures. Special attention is given to industrial and mission-critical applications of PCI bus.
·Fully describes PCI electrical specifications, mechanical requirements, and signal types
·Covers advanced topics through numerous design examples to increase the readers understanding of the subject
·Includes updated coverage of PCI-X 2.0
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10 Hot Plug and Hot Swap
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add-in card address phase agent asserted Attribute Phase backplane Base Address Register Base and Limit bridge buffers bus master bus number bus segment busses Byte Count byte enables C/BE clock cycle CompactPCI computer bus Configuration Space configuration transaction connector controller conventional PCI data phase deasserted decode defined detects device driver Device Number DEVSEL DWORD Expansion ROM FRAME GND GND GND Open Hot Plug System Hot Swap IDSEL implement initiator Input interface interrupt IRDY Latency Latency Timer LOCK master maximum Memory Read Message Signaled Interrupt Open GND Open Open operating optional output parameters parity error PCI bus PCI specification PCI-X Mode PCIXCAP PICMG prefetchable processor protocol pull-up resistors read-only request Reserved resistor secondary bus signaling environment slew rate source synchronous Special Cycle Split Completion Status Register STROBE Switching System Management Bus system slot Table target terminate TRDY Type vendor Voltage Vout
Page 9 - PERR# Parity error reports a data parity error on all commands except special cycles. SERR# System error reports address parity errors, data parity errors on special cycle commands, or any other system error where the result would be catastrophic. Interface Control FRAME* Cycle frame is driven by the current master to indicate the beginning and duration of an access. TRDY# Target ready indicates the target agent's, (selected device's), ability to complete the current data phase of the transaction....
Page 10 - For reporting data Parity Errors during all PCI transactions except a Special Cycle.
Page 7 - PCI interface requires a minimum of 47 pins for a target-only device and 49 pins for a master.