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ContextAware Process Networks
MultiDimensional Incremental Loop Fusion for Data Locality
Switched Memory Architectures Moving Beyond Systolic Arrays
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adder addition algorithm applications ARC unit architecture arithmetic array binary bits block block cipher butterfly bypass paths Cayley graph channel circuit clock cycles CMSSUs compiler complexity computation configuration constraints CORDIC curves data transfers dataflow decimal decoder delay dependence devices digit DS-CDMA efficient encryption Equation execution floorplan FPGA functional units graph hardware IEEE implementation input instruction set integer interconnection iteration latency linear LNS unit logic loop loop fusion mapping matrix memory accesses method modular multiplication modules modulo motion estimation node operands operations optimized output parallel partial product path metric performance permutation pipeline FFT polynomial processor producer proposed RAKE receiver reconfigurable reconfigurable computing reduced redundant register file rotation S-box schedule Section shown in Figure simulation stage step superscalar switch systolic array Table techniques transformation TriMedia two's complement vector Viterbi decoder VLIW VLSI