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MacroBased Hardware Compilation of Java Bytecodes into a Dynamic
A CAD Suite for HighPerformance FPGA Design
Formal Verification of Reconfigurable Cores
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adaptive computing adder algorithm allows application approach architecture array bits block buffer cache chip circuit CLBs clock cycle coefficients compiler configurable hardware coprocessor core CPLD Custom Computing Machines custom instructions debugging design rule checking design rules developed devices dynamic reconfiguration elements example execution Field Programmable FIFO filter formal verification FPGA function graph IEEE implementation input interface iterations JHDL layer loop loop tiling mapping memory merge module multiplier NENYA netlist node operations optimal output packet Pamette parallel partitioning performance pipeline PipeRench pixel place and route polygon precision Proc processor reconfigurable computing registers router routing RPEs run-time reconfiguration schedule Section shown in Figure signal simulation specific SRAM structure synthesis Table techniques tion variable vector VHDL Virtex virtual VLSI wires Xilinx