IEEE Computer Society, 1999 - Computers - 299 pages
The program for this November 1999 conference continues discussions MICRO has encouraged throughout the 1990s on advancements in microarchitectures and compilation techniques. These proceedings include the Keynote address by Fred Pollack, an Intel Fellow and Director of the Microprocessor Research Labs. The sessions cover topics such as 3D and multimedia, efficient embedded processors, memory hierarchy, novel microarchitectures and multithreading, and low power enhancements. No subject index. Annotation copyrighted by Book News, Inc., Portland, OR.
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New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies
Fetch Directed Instruction Prefetching
Improving Branch Predictors by Correlating on Data Values
17 other sections not shown
algorithm applications approach ARPT average bandwidth basic block benchmarks bound branch instruction branch prediction cache block cache line cache miss cache ports CodePack compiler compression Computer Architecture configuration conflict misses control flow control independence core processor cycle data cache decode detected dilation DIVA checker dynamic entry evaluation execution exploit fetch blocks FGCI Figure FPGA graphics hardware heuristic IEEE implementation input instruction cache instruction fetch instruction prefetching instruction window integer L2 cache latency load logic loop MDMX mechanism memory dependence Microarchitecture microprocessors multipath multithreaded operand operations optimizations out-of-order parallelism path performance physical registers pipeline pixel PowerPC predictor Proc RAR dependence reduce region register file reuse scheduling scheme Section shows simulation speculative Speculative Multithreaded speedup store instructions superblock superscalar Symp Table target techniques thread tion TLB miss triangles value prediction vector VLIW VLIW processor