Proceedings of PART '98: The 5th Australasian Conference on Parallel and Real-Time Systems : University of Adelaide, Adelaide, Australia, 28-29 September 1998
The proceedings of the 5th Australasian Conference on Parallel and Real-Time Systems (PART '98) collects some of the exciting and innovative approaches to the problems of high performance computing. At a time when the field is going through a shake-out of commercial solutions, the research presented here gives an insight into new hardware, software and algorithms for achieving high-performance on parallel and reconfigurable computing systems. PART '98 covers networking and processing hardware innovations; network traffic simulation, modeling and routing algorithms; operating systems software and control methods; and parallel algorithms and applications. Special emphasis is on algorithms for managing data and memory and reconfigurable systems. Articles describe activities at both overview level as well as highly technical mathematical analyses of some algorithmic approaches.
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RealTime Systems Design and Specification
Allen Leung Krishna V Palem and Amir Pnueli
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abstract address space algorithm allocation AntNet application architecture array assignment Australia block buffer cache circuit communication Computer configuration constraints cost data parallel defined delay digits distributed domain DSM system dynamically reconfigurable elements execution Figure FPGA functional density garbage collection global graph grid graph Hamiltonian cycle Hamiltonian path hardware heap segments IEEE implementation initial input instructions integrated interprocess interprocess communication iteration kernel L4Linux language Linux load logic loop machine mapping matrix mesh method microkernel multi-mesh multiplier node number of processors object operating system optimal OSPF output packets parallel computer partitioning performance permutation Pr/T-Net problem processor queue real-time reconfigurable computing RHODOS router routing scheduling Section server specification steps structure switched systolic arrays tasks technique Temporal Logic throughput tile TimeC tion traffic University of Adelaide values variables vector vertices wavelength workstations Xilinx