What people are saying - Write a review
We haven't found any reviews in the usual places.
A Mechanism for Exploiting FarFlung ILP in Ordinary Programs
Speculation Techniques for Improving Load Related Instruction Scheduling
13 other sections not shown
address predictor Annual International Symposium applications bandwidth benchmarks bits block cache branch prediction cache line cache misses check code coherence Compensation Code compiler Computer Architecture configuration counter cycle data cache dependence detection disambiguation DRAM dynamic entry execution fetch block Figure FPGAs hardware hot spot I-cache IEEE improve increase instruction window issue jump-pointer L2 cache latency load instructions loop machine mechanism memory access memory disambiguation memory hierarchy memory latency memory model memory operations memory system Microarchitecture microprocessors microthread misprediction multiple node operands optimizations out-of-order overhead parallelism parity cache performance pipeline pointer predicate define predicted value prefetching processor protocol queue Rambus RC implementations reduce renaming reorder buffer request requires SC++ scheduling scheme Section SHiQ shows simulation speculative speculative execution speedup stall static stripe superscalar Symposium on Computer techniques tion trap updated value prediction vector trace VLIW