Proceedings of the International Conference on Application Specific Array Processors: August 4-7, 1992, Berkeley, California
Josť Fortes, Edward A. Lee, Teresa Meng, Industrial Development Board for Northern Ireland, IEEE Computer Society
IEEE Computer Society Press, 1992 - Computers - 698 pages
Very Good,No Highlights or Markup,all pages are intact.
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Hierarchical Scheduling of DSP Programs onto Multiprocessors
Linear Scheduling is Close to Optimality
On Systolic Mapping of MultiStage Algorithms
41 other sections not shown
algorithm allocation application architecture Array Processors bandwidth beamformer binary block broadcast buffers chip circuit column communication complexity components computation constraints CORDIC corresponding data flow decoder defined delay dependence graph dependence vectors described developed digital signal processing efficient equations estimation example execution FIFO filter flow graph function given hardware hyperplane IEEE implementation index space input vector integer interconnection interface interval interval graph latency linear loop LPGS mapping matrix memory memory segments method modules multi-chip module multiple multiprocessor neural node number of processors operations optimal output parallel Parallel Computing parameters partitioning path performance pipelining problem Proc processing elements processor array quantization real-time recurrence scheduling sequence shown in Figure SIMD simulation SPERT stage stored structure subtask supercell synthesis systolic array task techniques Theorem throughput transformation update variables vector quantization VLSI