Processor Architecture: From Dataflow to Superscalar and Beyond ; with 34 Tables

Front Cover
Springer Science & Business Media, Jun 8, 1999 - Architecture - 389 pages
Today's microprocessors are the powerful descendants of the von Neumann 1 computer dating back to a memo of Burks, Goldstine, and von Neumann of 1946. The so-called von Neumann architecture is characterized by a se quential control flow resulting in a sequential instruction stream. A program counter addresses the next instruction if the preceding instruction is not a control instruction such as, e. g. , jump, branch, subprogram call or return. An instruction is coded in an instruction format of fixed or variable length, where the opcode is followed by one or more operands that can be data, addresses of data, or the address of an instruction in the case of a control instruction. The opcode defines the types of operands. Code and data are stored in a common storage that is linear, addressed in units of memory words (bytes, words, etc. ). The overwhelming design criterion of the von Neumann computer was the minimization of hardware and especially of storage. The most simple implementation of a von Neumann computer is characterized by a microar chitecture that defines a closely coupled control and arithmetic logic unit (ALU), a storage unit, and an I/O unit, all connected by a single connection unit. The instruction fetch by the control unit alternates with operand fetches and result stores for the AL U.
 

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Contents

1 Basic Pipelining and Simple RISC Processors
1
12 Instruction Set Architecture
5
13 Examples of RISC ISAs
10
14 Basic Structure of a RISC Processor and Basic Cache MMU Organization
15
15 Basic Pipeline Stages
18
16 Pipeline Hazards and Solutions
22
161 Data Hazards and Forwarding
23
162 Structural Hazards
27
49 StateoftheArt Superscalar Processors
168
492 AMDK5 K6 and K7 families
175
493 Cyrix M II and M 3 Processors
178
495 Sun UltraSPARC family
184
496 HAL SPARC64 family
187
497 HP PA7000 family and PA8000 family
190
498 MIPS R10000 and descendants
195
499 IBM POWER family
199

163 Control Hazards Delayed Branch Technique and Static Branch Prediction
28
164 Multicycle Execution
30
17 RISC Processors
32
171 Early Scalar RISC Processors
33
172 Sun microSPARCII
34
173 MIPS R3000
38
174 MIPS R4400
40
175 Other Scalar RISC Processors
43
176 Sun picoJavaI
46
18 Lessons learned from RISC
53
2 Dataflow Processors
55
22 Pure Dataflow
58
221 Static Dataflow
59
222 Dynamic Dataflow
63
223 Explicit Token Store Approach
72
23 Augmenting Dataflow with ControlFlow
77
231 Threaded Dataflow
78
232 LargeGrain Dataflow
85
233 Dataflow with Complex Machine Operations
88
234 RISC Dataflow
90
235 Hybrid Dataflow
93
24 Lessons learned from Dataflow
95
3 CISC Processors
99
32 OutofOrder Execution
100
33 Dynamic Scheduling
101
332 Tomasulos Scheme
109
333 Scoreboarding versus Tomasulos Scheme
117
34 Some CISC Microprocessors
118
35 Conclusions
120
4 MultipleIssue Processors
123
42 ICache Access and Instruction Fetch
129
43 Dynamic Branch Prediction and Control Speculation
130
431 BranchTarget Buffer or BranchTarget Address Cache
132
432 Static Branch Prediction Techniques
133
433 Dynamic Branch Prediction Techniques
134
434 Predicated Instructions and Multipath Execution
146
435 Prediction of Indirect Branches
150
436 HighBandwidth Branch Prediction
151
44 Decode
152
45 Rename
153
46 Issue and Dispatch
155
47 Execution Stages
159
48 Finalizing Pipelined Execution
164
482 Precise Interrupts
165
483 Reorder Buffers
166
484 Checkpoint Repair Mechanism and History Buffer
167
4911 Summary
203
4101 TI TMS320C6x VLIW Processors
207
4102 EPIC Processors Intels IA64 ISA and Merced Processor
212
411 Conclusions on MultipleIssue Processors
217
5 Future Processors to use FineGrain Parallelism
221
512 Application and EconomyRelated Trends
223
513 Architectural Challenges and Implications
224
52 Advanced Superscalar Processors
227
53 Superspeculative Processors
231
54 Multiscalar Processors
234
55 Trace Processors
239
56 DataScalar Processors
242
57 Conclusions
245
6 Future Processors to use CoarseGrain Parallelism
247
62 Chip Multiprocessors
248
622 TI TMS320C8x Multimedia Video Processors
252
623 Hydra Chip Multiprocessor
254
63 Multithreaded Processors
257
632 Comparison of Multithreading and NonMultithreading Approaches
260
633 CyclebyCycle Interleaving
262
634 Block Interleaving
269
635 Nanothreading and Microthreading
280
64 Simultaneous Multithreading
281
641 SMT at the University of Washington
282
642 Karlsruhe Multithreaded Superscalar
284
643 Other Simultaneous Multithreading Processors
292
65 Simultaneous Multithreading versus Chip Multiprocessor
293
66 Conclusions
297
7 ProcessorinMemory Reconfigurable and Asynchronous Processors
299
712 ProcessorinMemory approaches
303
713 The Vector IRAM approach
305
714 The Active Page model
306
72 Reconfigurable Computing
307
722 The MorphoSys system
313
723 Raw Machine
315
724 Xputers and KressArrays
318
725 Other Projects
321
73 Asynchronous Processors
323
731 Asynchronous Logic
325
732 Projects
328
74 Conclusions
333
Acronyms
335
Glossary
343
References
361
Index
379
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