What people are saying - Write a review
We haven't found any reviews in the usual places.
Formal Techniques for Hardware Correctness
PlaceRouter for Seaof Gates Design Style
Multilayer Routing Problem
7 other sections not shown
Other editions - View all
1-D systolic array algorithm applied approach axioms basic cell Boolean candidate set capacitances channel chip closed area column complexity connection length convergence defined delay density Design Automation Conference device models dynamic efficient electronic circuit simulation equations example first-order predicate calculus first-order predicates formal system formal verification functional cells gate global routing hardware horizontal constraints IEEE Transactions implementation input Integrated Circuits intersection graph iteration layer assignment layout leaf nodes linear list mapping matrix method minimal modules MOSFET nets Newton-Raphson nonfaulty nonlinear objective function optimal output path graph pins placement position procedure routability router routing problem rows Section selection shown in Figure simulated annealing simulator program slice solution solving specification SPICE step structure subcircuit switchbox systolic array technique temporal logic theorem tion topology Transactions on Computers transformation transistor variables vector vertical constraints VLSI voltage drop waveform weak division width wire segments