This book covers the principles and techniques that make RISC a unique and elegant approach for high-performance microprocessor system designs, describing both the practical and theoretical aspects of the RISC design philosophy.
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Principles of the RISC design methodology
Overview of RISC microprocessors
the KIM20 microprocessor
3 other sections not shown
addressing modes arithmetic and logical Berkeley RISC branch instructions buffer byte cache memory cell CISC clock cycle CMOS CMOS VLSI codes C Unmodified compiler complexity coprocessor cycles per instruction data-path decode exception pc destination register Rd exception handling Execution scheme execution units Fetch decode exception Floating-Point Unit Format Code-op GaAs hardware high-level language IEEE implementation instruction execution instruction fetch instruction format instruction set integer interrupt jump Lisp load and store machine main memory memory access Memory Management Unit microcode microprocessor MIPS Computer Systems MIPS-X multiply number of clock OPCODE operands optimizing otherwise cleared performance pointer Rd S1 S2 read S1 register file register windows result RISC architecture RISC design RISC-I scheme I CLOCK sequence source operands source register SPARC stack Status Word subtract superscalar Syntax Operation Description transputer trap unsigned Write Rd xxxx xxxx 31 xxxx xxxx xxxx xxxxx XXXXX