What people are saying - Write a review
We haven't found any reviews in the usual places.
RISC Advantages and Shortcomings
The Berkeley RISC
The Stanford and Commercial MIPS
11 other sections not shown
32 bits 64 KBytes address space addressing modes Architecture Arithmetic benchmark Berkeley RISC block diagram byte called chapter chip CISC CLIPPER clock CMOS compiler Computer Design configuration contains Control Register control unit Coprocessor Courtesy CPU register CPU register file cycle data cache Data Memory decoding execution Fetch Floating Point Unit Floating-Point GBytes half word hardware IEEE illustrated in Figure implemented Input instruction formats instruction pipeline Instruction Set integer interface Interrupt Load Load/Store Logical machine Macro main memory memory access Memory Management Unit MFLOPS Micro Microprocessor MIPS Computer Systems MIRIS Motorola Multiply multiprocessor MULTRIS OESCRIPtOR on-chip OPCODE operand operation performance pipeline procedure Program Counter register file register set register window RISC systems RISC-type systems shown in Figure signals single SPARC src2 stack Status Register Store subroutine subsystem Table Technology Transputer trap Unix Unsigned Vector VLSI workstations