Reduced Instruction Set Computer (RISC) technology is advancing at a rapid pace, even since publication of the author's RISC Architecture in 1987. This work fills the need for a text that presents the state of the art in RISC technology, highlighting the latest and most important design methodologies that RISC technology has made possible. Serving advanced students, as well as practicing engineers and computer scientists. Presents the basic principles and properties of RISC, discusses its advantages and disadvantages, and describes RISC applications. A number of leading commercial and experimental RISC systems, which are themselves compared and evaluated, are also covered. Several chapters are devoted to a specific manufacturer and its system, and the results of numerous comparative experimental runs of standard benchmark problems are presented, along with evaluative discussions. Numerous problems, basic definitions and a glossary of abbreviations are also included.
What people are saying - Write a review
We haven't found any reviews in the usual places.
RISC Advantages and Shortcomings
The Berkeley RISC
The Stanford and Commercial MIPS
11 other sections not shown
32 bits 64 KBytes address space addressing modes Architecture Arithmetic benchmark Berkeley RISC block diagram byte called chapter chip CISC CLIPPER clock CMOS compiler configuration contains Control Register control unit Coprocessor Courtesy CPU register CPU register file cycle Data Cache Data Memory decoding Fetch Floating Point Unit Floating-Point GBytes Halfword hardware IEEE illustrated in Figure implemented Input instruction formats instruction pipeline Instruction Set integer interface Interrupt Load Load/Store Logical machine Macro main memory memory access Memory Management Unit MFLOPS Micro Microprocessor MIPS Computer Systems MIRIS Motorola Multiply multiprocessor MULTRIS OESCRIPTOR on-chip opcode operand operation performance procedure Processor Status Program Counter purpose registers register file register set register window RISC systems RISC-type systems shown in Figure signals single SPARC src2 stack Status Register Store subroutine subsystem Table Technology Transputer trap Unix Unsigned Vector VLSI workstations