Reconfigurable Computing: Architectures, Tools and Applications: 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010, Proceedings

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Phaophak Sirisuk, Fearghal Morgan, Tarek El-Ghazawi, Hideharu Amano
Springer Science & Business Media, Mar 17, 2010 - Computers - 446 pages
Recon?gurable computing (RC) systems have generated considerable interest in the embedded and high-performance computing communities over the past two decades, with ?eld programmable gate arrays (FPGAs) as the leading techn- ogy at the helm of innovation in this discipline. Achieving orders of magnitude performance and power improvements using FPGAs over traditional microp- cessorsis not uncommon for well-suitedapplications. But even with two decades of research and technological advances, FPGA design still presents a subst- tial challenge and often necessitates hardware design expertise to exploit its true potential. Although the challenges to address the design productivity - sues are steep, the promise and the potential of the RC technology in terms of performance, power, size, and versatility continue to attract application design engineers and RC researchers alike. The International Symposium on Applied Recon?gurable Computing (ARC) aims to bring together researchers and practitioners of RC systems with an emphasis on practical applications and design methodologies of this promising technology. This year’s ARC symposium (The sixth ARC symposium) was held in Bangkok, Thailand during March 17–19, 2010, and attracted papers in three primary focus areas:RC applications, RC architectures, and RC design meth- ologies.
 

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Contents

HighPerformance EnergyEfficient Reconfigurable AcceleratorsCoprocessors for TeraScale Multicore Microprocessors
1
New Frontier for Reconfigurable
2
Towards Analytical Methods for FPGA Architecture Investigation
3
Generic Systolic Array for RunTime Scalable Cores
4
Virtualization within a Parallel Array of Homogeneous Processing Units
17
Feasibility Study of a Selfhealing Hardware Platform
29
ApplicationSpecific Signatures for Transactional Memory in Soft Processors
42
Towards Rapid Dynamic Partial Reconfiguration in VideoBased Driver Assistance Systems
55
QUAD A Memory Access Pattern Analyser
269
Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations
282
Reconfigurable Computing and Task Scheduling for Active Storage Service Processing
294
A Reconfigurable Disparity Engine for Stereovision in Advanced Driver Assistance Systems
306
A Modified Merging Approach for Datapath Configuration Time Reduction
318
Reconfigurable Computing Education in Computer Science
329
Hardware Implementation of the Orbital Function for Quantum Chemistry Calculations
337
Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing
343

Parametric Encryption Hardware Design
68
A Reconfigurable Implementation of the Tate Pairing Computation over GF2m
80
Application Specific FPGA Using Heterogeneous Logic Blocks
92
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip
110
A Dedicated Reconfigurable Architecture for Finite State Machines
122
MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment
134
An FPGA Accelerator for Hash Tree Generation in the Merkle Signature Scheme
145
A Fused Hybrid FloatingPoint and FixedPoint DotProduct for FPGAs
157
Optimising Memory Bandwidth Use for MatrixVector Multiplication in Iterative Methods
169
Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA
182
A Novel BlockingAware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices
194
A ReconfigurabilityAware FPGA Router
207
Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing
219
RoutingAware Application Mapping Considering Steiner Points for CoarseGrained Reconfigurable Architecture
231
Design Automation for Reconfigurable Interconnection Networks
244
A Framework for Enabling Fault Tolerance in Reconfigurable Architectures
257
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures
351
A GMMBased Speaker Identification System on FPGA
358
An FPGABased RealTime Event Sampler
364
OneDimensional 512 FPGA Cluster
372
An Analysis of Delay Based PUF Implementations on FPGA
382
Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor
388
FPGA Implementation of QR Decomposition Using MGS Algorithm
394
MemoryCentric Communication Architecture for Reconfigurable Computing
400
Integrated Design Environment for Reconfigurable HPC
406
ArchitectureAware Custom Instruction Generation for Reconfigurable Processors
414
Cost and Performance Evaluation of a Noise Filter for Partitioning in Codesign Methodologies
420
Towards a Tighter Integration of Generated and CustomMade Hardware
426
Pipelined Microprocessors Optimization and Debugging
435
Author Index
445
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