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FPGA implementation of image component labeling 384404
hardware objectoriented use and RC management system 384405
Toward an FPGA architecture optimized for publickey algorithms 384406
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adaptive adder addition algorithm Altera analog application arithmetic ASIC bitstream block buffers carry-save adders Chidi circuit CLBs clock co-processor complex components configuration connected cryptographic cycle devices display dither dynamic reconfiguration edge response feed-forward Field-Programmable FIFO FPAA FPGA FPGA architectures FPGA implementations frequency hardware object hologram host IEEE image processing input intensity similarity function interconnect label latency logic look-up table look-up-tables memory minimal resource set modular arithmetic modular multiplication Montgomery Reduction motor multiply-accumulate neighbourhood operation node output parallelism partitioning PCI interface performance pins pixel place and route placement PLDSP processing elements prototyping Qard Quick Qard reconfigurable computing reconfigurable processor registers router routing resources run-time reconfiguration segment shown in Figure signal simulation speed feedback module SRAM stored switch synthesis Systolic Array technique USAN VHDL Xilinx