Records of the IEEE International Workshop on Memory Technology, Design, and Testing, August 8-9, 1994, San Jose, California
IEEE Computer Society. Test Technology Technical Committee, IEEE Computer Society. Technical Committee on VLSI.
IEEE Computer Society Press, Aug 1, 1994 - Computers - 141 pages
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A SelfDiagnostic BIST Memory Design Scheme
An OnChip Test Scheme for SRAMs
Mechanical StressInduced Void Formation in Thin Films
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allocation applied architecture bit line bitline block cache memory CAM cell CAM/RAM checker circuit CMOS CMOS SRAM column Computer consumption current coupling faults cycle decoder faults detected device diffusion creep double-coupling fault dual-port RAMs dummy cell Failure Analysis fault coverage fault model fault-free FIFO films gate grain boundary hardware hillocks IEEE implementation input interconnect laser beam load logic logic value march element march tests match line matrix mega bit memory cell array memory coverage memory test method mode node output parameters performed polysilicon processor propagation delay radiation hardness random Random Access Memories read operation read/write scan self-test sense amplifier sequence shown in Figure signal SMARCH soft error SRAM cell SRAM chip storage cell stuck-at faults test algorithm test patterns testability transistor transition V-coupling voltage word line workstation write operation XOR gate