Register renaming and dynamic speculation: an alternative approach
Mayan Moudgill, Keshav Pingali, Stamatis Vassiliadis, Cornell Theory Center. Advanced Computing Research Institute
Center for Theory and Simulation in Science and Engineering, Cornell University, 1993 - Computers - 32 pages
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architected register architecture associative lookup branch is resolved branch prediction cache CMOS complete flag considered unmapped content-addressable storage counter critical path current map cycle-time described DRIS dynamic speculation entry fanout floating point floating-point floating-point unit free physical register free pool free register freed hardware history buffer implements register renaming in-order file in-order map instruction completes instruction decode stage instruction fetch stage instruction is added instruction-level parallelism instruction's instructions issued instructions prior keep track map is updated Map rl map save stack map save table mapping logic mapping table Microprocessor mispredicted branch old physical register out-of-order execution output register name physical register allocated physical register mapped pipeline program order queue reclaimed register file remapped reorder buffer reservation stations result register reused saved map scheme set to true slot source register name speculate past speculation and precise speculative instructions superscalar processor tag match logic unmap flag upto value produced