Scalable Shared Memory Multiprocessors: Proceedings
Michel Dubois, S. S. Thakkar
Springer Science & Business Media, 1992 - Computers - 329 pages
The workshop on Scalable Shared Memory Multiprocessors took place on May 26 and 27 1990 at the Stouffer Madison Hotel in Seattle, Washington as a prelude to the 1990 International Symposium on Computer Architecture. About 100 participants listened for two days to the presentations of 22 invited The motivation for this workshop was to speakers, from academia and industry. promote the free exchange of ideas among researchers working on shared-memory multiprocessor architectures. There was ample opportunity to argue with speakers, and certainly participants did not refrain a bit from doing so. Clearly, the problem of scalability in shared-memory multiprocessors is still a wide-open question. We were even unable to agree on a definition of "scalability". Authors had more than six months to prepare their manuscript, and therefore the papers included in this proceedings are refinements of the speakers' presentations, based on the criticisms received at the workshop. As a result, 17 authors contributed to these proceedings. We wish to thank them for their diligence and care. The contributions in these proceedings can be partitioned into four categories 1. Access Order and Synchronization 2. Performance 3. Cache Protocols and Architectures 4. Distributed Shared Memory Particular topics on which new ideas and results are presented in these proceedings include: efficient schemes for combining networks, formal specification of shared memory models, correctness of trace-driven simulations,synchronization, various coherence protocols, .
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address space Alewife algorithm Annual International Symposium bit vector burst throughput cache coherence cache coherence protocol cache line coarse vector coherence protocol combining tree combining window Computer Architecture consistency protocol context switch copy copyset critical section cycle data words directory entry directory memory directory protocol directory scheme distributed shared memory efficient ELPS Figure full bit vector full-map global trace hardware IEEE implementation increase interconnect invalidations large number latency Load lock machine main memory memory access memory block memory coherence memory modules memory operations memory system Michel Dubois multicomputer multiprocessor multithreaded Munin number of processors overhead page fault parallel programs performance physical pointer Proceedings process migration queue reduce remote request rate scalable sequential consistency shared data shared memory multiprocessors shared virtual memory sharing list simulator sparse directories Store Swap Symposium on Computer Table thread traffic transactions transfer unit update write