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TABLE 21 PRIVILEGED INSTRUCTIONS 219
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32 bits AAAAAAAA access class address space address specified address translation addressing mode architecture assembly language Basic instruction binary bit field bit position Breakpoint byte of register CFG register cleared otherwise Cont data type dest gen gen dest operand location disp disp2 Dispatch Table double-word effective address encoded Example execution Flags Affected Frame Pointer gen gen read.i Index Byte instruction is illustrated instruction set integer interrupt length attribute Link table logical address logical address space low-order byte memory address Memory Management offset Operand Values Hex Operands Operand Values operation length page table physical address places the result Processor Register Program Counter Purpose registers register R0 rmw.i Scaled Indexing segment signed integer Slave Processor src dest src gen src operand Stack Pointer Status register String Supervisor mode Syntax table entry Top-of-Stack Unaffected UPSR Values Hex Dec virtual address virtual memory xxxxxxxx zero